Light receiving device and light receiving method

ABSTRACT

A light receiving device includes: a converter digitalizing an analog signal with a given sampling clock frequency, the analog signal being obtained through a photoelectric conversion of a received optical signal; a plurality of fixed distortion compensators compensating an output signal of the converter for waveform distortion with a fixed compensation amount that is different from each other; a plurality of phase shift detector circuits detecting a sampling phase shift from an output signal of the plurality of the fixed distortion compensators; a phase-adjusting-amount determiner determining a sampling phase adjusting amount with use of an output signal of the plurality of the phase shift detector circuits; and a phase adjusting circuit reducing a phase difference between the sampling clock frequency and the received optical signal based on a determination result of the phase-adjusting-amount determiner.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2010-003246, filed on Jan. 8,2010, the entire contents of which are incorporated herein by reference.

FIELD

A certain aspect of embodiments described herein relates to a lightreceiving device and a light receiving method.

BACKGROUND

There is a demand for a main line optical communication system having ahigh capacity, because an internet traffic is increased. An opticalsignal to noise ratio (OSNR) tolerance is degraded when a bit rate perone wavelength is enlarged. In this case, a signal quality may bedegraded more because of chromatic dispersion of a transmission path,polarization mode dispersion, waveform distortion caused by non-lineareffect or the like. Therefore, a digital coherent receiving method hasattracted attention because the method is expected to improve the OSNRtolerance and waveform distortion tolerance of a transmission path. D.Ly-Gagnon, IEEE JLT, vol. 24, pp. 12-21, 2006 discloses the method.

The digital coherent receiving method is a method where opticalintensity and phase information are extracted with a coherent receivingmethod, and the extracted optical intensity and the extracted phaseinformation are digitalized by analog-to-digital convertor (ADC), andthe received signal is demodulated in a digital signal processingcircuit by digitalized signal. The digital coherent receiving method hasfavorable characteristics with respect to a high-bit-rate opticaltransmission, because the digital coherent receiving method improves theOSNR tolerance with the coherent receiving method and compensates forwaveform distortion with the digital signal processing circuit.

However, Darko Zibar et al, ECOC 2009, 7.3.4 discloses that the digitalcoherent receiving method has a problem that a sampling phase shiftdetector circuit has a low tolerance to waveform distortion caused bychromatic dispersion, polarization mode dispersion or the like, althoughthe digital coherent receiving method has high performance with respectto waveform distortion compensation with a digital signal processing.Especially, P. M. Krummrich et. al, OFC 2004, FI3 discloses that thepolarization mode dispersion of a transmission of a path fluctuatesspeedily because of fluctuation of polarization condition of thetransmission path. There is a demand for a sampling phase shiftdetecting method that may tolerate fluctuation of polarization modedispersion in operation and has high tolerance with respect to thewaveform distortion.

SUMMARY

According to an aspect of the present invention, there is provided alight receiving device comprising: a converter digitalizing an analogsignal with a given sampling clock frequency, the analog signal beingobtained through a photoelectric conversion of a received opticalsignal; a plurality of fixed distortion compensators compensating anoutput signal of the converter for waveform distortion with a fixedcompensation amount that is different from each other; a plurality ofphase shift detector circuits detecting a sampling phase shift from anoutput signal of the plurality of the fixed distortion compensators; aphase-adjusting-amount determiner determining a sampling phase adjustingamount with use of an output signal of the plurality of the phase shiftdetector circuits; and a phase adjusting circuit reducing a phasedifference between the sampling clock frequency and the received opticalsignal based on a determination result of the phase-adjusting-amountdeterminer.

According to an aspect of the present invention, there is provided alight receiving device comprising: a converter digitalizing an analogsignal with a given sampling clock frequency, the analog signal beingobtained through a photoelectric conversion of a received opticalsignal; a plurality of fixed distortion compensators compensating anoutput signal of the converter for waveform distortion with a fixedcompensation amount that is different from each other; a plurality ofcompensation amount detector detecting a distortion compensation amountbased on a phase-shift-detection sensitivity of each output signal ofthe plurality of the fixed distortion compensators; a distortioncompensator compensating for distortion with a distortion compensationamount detected by the compensation amount detector; aphase-adjusting-amount determiner determining a sampling phase adjustingamount with use of an output signal of the phase shift detector circuit;and a phase adjusting circuit reducing a phase difference between thesampling clock frequency and the received optical signal based on adetermination result of the phase-adjusting-amount determiner.

According to an aspect of the present invention, there is provided alight receiving method comprising: digitalizing an analog signal with agiven sampling clock frequency, the analog signal being obtained througha photoelectric conversion of a received optical signal; compensating anoutput signal obtained in the digitalizing for waveform distortion witha fixed compensation amount that is different from each other; detectinga sampling phase shift from each output signal obtained in thecompensating; determining a sampling phase adjusting amount with use ofan output signal obtained in the detecting; and reducing a phasedifference between the sampling clock frequency and the received opticalsignal based on a determination result of the determining.

According to an aspect of the present invention, there is provided alight a light receiving method comprising: digitalizing an analog signalwith a given sampling clock frequency, the analog signal being obtainedthrough a photoelectric conversion of a received optical signal;compensating an output signal obtained in the digitalizing for waveformdistortion with a fixed compensation amount that is different from eachother; detecting a distortion compensation amount based on aphase-shift-detection sensitivity of each output signal obtained in thecompensating for the waveform; compensating for distortion with adistortion compensation amount detected in the detecting; determining asampling phase shift amount with use of an output signal obtained in thecompensating for the distortion; and reducing a phase difference betweenthe sampling clock frequency and the received optical signal based on adetermination result of the determining.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims. It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a block diagram of a light receiving device inaccordance with a first embodiment;

FIG. 2 illustrates a flowchart of an example of an operation of thelight receiving device;

FIG. 3 illustrates a block diagram for describing details of a phaseshift detector;

FIGS. 4A and 4B illustrate details of fixed distortion compensation;

FIGS. 5A through 5K visually illustrate chromatic dispersioncompensation;

FIG. 6 illustrates an example of a fixed distortion compensator;

FIG. 7 illustrates a block diagram of a phase shift detector circuit;

FIG. 8 illustrates a block diagram for describing details of a FIR typephase adjusting circuit;

FIGS. 9A through 9C illustrate a sensitivity detector detectingsensitivity with use of a phase shift detector circuit;

FIG. 10 illustrates a block diagram of a phase shift detector inaccordance with a second embodiment;

FIG. 11 illustrates a block diagram of a modified embodiment of thesecond embodiment;

FIG. 12 illustrates a block diagram of a light receiving device inaccordance with a third embodiment; and

FIG. 13 illustrates a block diagram of a light receiving device inaccordance with a fourth embodiment.

DESCRIPTION OF EMBODIMENTS

The following is a description of embodiments of the present invention,with reference to the accompanying drawings.

[a] First Embodiment

FIG. 1 illustrates a block diagram of a light receiving device 100 inaccordance with a first embodiment. As illustrated in FIG. 1, the lightreceiving device 100 includes a 90 degrees hybrid circuit 10, a localoscillation light source 20, a photoelectric conversion circuits 30 athrough 30 d, an analog/digital converters 40 a through 40 d, a phaseadjusting circuit 50, a detector circuit 60, a sampling clock source 70,a phase shift detector 80, and a phase-adjusting-amount determiner 90.

FIG. 2 illustrates a flowchart of an example of an operation of thelight receiving device 100. A description will be given of an outline ofthe operation of the light receiving device 100 with reference to FIG. 1and FIG. 2. The 90 degrees hybrid circuit 10 receives a received opticalsignal fed into the light receiving device 100 and a local oscillationoptical signal output by the local oscillation light source 20.

The 90 degrees hybrid circuit 10 mixes the received optical signal andthe local oscillation optical signal per two polarized waves at rightangles to each other, and outputs an optical signal of a real part(I-phase) and an imaginary part (Q-phase) of polarized waves (Hpolarized wave and V polarized wave) (Step S1).

The photoelectric conversion circuits 30 a through 30 d convert theoptical signals of an I-phase signal and a Q-phase signal of twopolarized waves at right angles to each other into an electrical signal(Step S2). In the embodiment, the photoelectric conversion circuit 30 aconverts the H-I signal into an electrical signal. The photoelectricconversion circuit 30 b converts the H-Q signal into an electricalsignal. The photoelectric conversion circuit 30 c converts the V-Isignal into an electrical signal. The photoelectric conversion circuit30 d converts the V-Q signal into an electrical signal.

The analog/digital converters 40 a through 40 d convert an outputelectrical signal of the photoelectric conversion circuits 30 a through30 d into a digital signal in accordance with a timing (samplingfrequency) of an input signal from the sampling clock source 70, andinputs the digital signal into the phase adjusting circuit 50 (Step S3).The phase adjusting circuit 50 adjusts a sampling phase of the digitalsignals output by the analog/digital converters 40 a through 40 d andoutputs the adjusted digital signal. The phase shift detector 80 detectsa phase shift (phase error) between a modulation frequency of thereceived optical signal and the sampling frequency with use of theoutput signal of the phase adjusting circuit 50 (Step S4). Thephase-adjusting-amount determiner 90 determines a sampling phaseadjusting amount based on the phase shift obtained in Step S4 (Step S5).The phase adjusting circuit 50 adjusts the sampling phase based on thesampling phase adjusting amount obtained in Step S5, and inputs theadjusted signal into the detector circuit 60 (Step S6). The detectorcircuit 60 is a digital coherent detector circuit including a waveformequalizer, a decoder, an error corrector and so on, and demodulates theinput digital signal (Step S7).

A description will be given of each portion. FIG. 3 illustrates a blockdiagram for describing details of the phase shift detector 80. Asillustrated in FIG. 3, the phase shift detector 80 has n (“n” is aninteger and is two or more) number of fixed distortion compensators 81having a compensation amount that is different from each other, n numberof phase shift detector circuits 82, and a combining circuit 83. Eachfixed distortion compensator 81 receives four signals of the H-I signal,the H-Q signal, the V-I signal and the V-Q signal.

Each phase shift detector circuit 82 is a sampling phase shift detectorcircuit detecting the sampling phase shift at the sampling clock source70, and is provided according to each fixed distortion compensator 81.In concrete, an output signal of a first fixed distortion compensator 81is input into a first phase shift detector circuit 82. An output signalof a n-th fixed distortion compensator 81 is input into a n-th phaseshift detector circuit 82. Each phase shift detector circuit 82 detectsthe sampling phase shift based on the output signal of each fixeddistortion compensator 81, and inputs the detection result into thecombining circuit 83.

Each fixed distortion compensator 81 is a distortion compensator circuithaving a compensation amount that is different from each other.Therefore, waveform distortion amount of a signal output by the fixeddistortion compensator circuit is different from each other according tothe waveform distortion amount of the received optical signal. That is,the output signal of the fixed distortion compensator circuit having areverse compensation amount with respect to waveform distortion of thereceived optical signal is a signal without waveform distortion. Theoutput signal of the fixed distortion compensator circuit having acompensation amount that is difference from the reverse compensationamount with respect to the waveform distortion of the received opticalsignal is a signal having a large waveform distortion.

This allows inputting of a signal having a small waveform distortioninto at least one of the n number of sampling phase shift detectorcircuits. Thus, it is possible to detect an adequate sampling phaseshift amount even if the waveform distortion of the received opticalsignal is large.

The combining circuit 83 is a circuit averaging the input signals. Thecombining circuit 83 may be a circuit that simply averages the inputsignals or a circuit that weighted-averages the input signals.

The combining circuit 83 inputs information concerning a phase shiftobtained by the averaging into the phase-adjusting-amount determiner 90.The phase-adjusting-amount determiner 90 determines the sampling phaseadjusting amount through a calculation or the like based on theinformation concerning the phase shift. The phase adjusting circuit 50adjusts the sampling phase of the output digital signals of theanalog/digital converters 40 a through 40 d to the sampling phasedetected based on the phase-adjusting-amount determiner 90. The phaseadjusting circuit 50 therefore can reduce the difference between thesampling phase of the sampling clock source 70 and the modulationfrequency of the received optical signal. That is, the phase adjustingcircuit 50 can reduce the sampling phase shift.

Next, a description will be given of details of the fixed distortioncompensation. FIG. 4A illustrates a block diagram for describing detailsof a FIR (Finite Impulse Response) type of the fixed distortioncompensator 81. As illustrated in FIG. 4A, for example, the FIR type ofthe fixed distortion compensator 81 has a first multiplication portion11, a second multiplication portion 12, a third multiplication portion13, a first delay portion 14, a second delay portion 15, and an additionportion 16. The first multiplication portion 11, the secondmultiplication portion 12 and the third multiplication portion 13 have afixed multiplication coefficient that is different from each other.

The first delay portion 14 sets a predetermined delay amount on an inputsignal to the fixed distortion compensator 81 and outputs the inputsignal having the delay. The second delay portion 15 sets apredetermined delay amount on the signal output by the first delayportion 14 and outputs the signal having the delay. The firstmultiplication portion 11 inputs a multiplication result between thesignal input to the fixed distortion compensator 81 and themultiplication coefficient of the first multiplication portion 11 intothe addition portion 16. The second multiplication portion 12 inputs amultiplication result between the signal output by the first delayportion 14 and the multiplication coefficient of the secondmultiplication portion 12 into the addition portion 16. The thirdmultiplication portion 13 inputs a multiplication result between thesignal output by the second delay portion 15 and the multiplicationcoefficient of the third multiplication portion 13 into the additionportion 16.

The addition portion 16 outputs a summation of the multiplicationresults of the first multiplication portion 11, the secondmultiplication portion 12 and the third multiplication portion 13. Withthe processes, the fixed distortion compensator 81 compensates forchromatic dispersion with respect to the input signal, when themultiplication coefficients of the first multiplication portion 11, thesecond multiplication portion 12 and the third multiplication portion 13are coefficients according to the chromatic dispersion.

It is assumed that a multiplication coefficient C1 is set in the firstmultiplication portion 11 fixedly, a multiplication coefficient C2 isset in the second multiplication portion 12 fixedly, and amultiplication coefficient C3 is set in the third multiplication portion13 fixedly. And, it is assumed that a delay amount Ts is set in thefirst delay portion 14 and the second delay portion 15 as a samplingtiming.

In this case, the coefficient according to the chromatic dispersion isshown as the following equation (1). In the equation (1), “f” is acarrier frequency, “C” is a light speed, “D” is a chromatic dispersioncompensation amount, “ω” is an angular frequency, and “j” is animaginary unit.

$\begin{matrix}{\left\lbrack {{Equation}\mspace{14mu} (1)} \right\rbrack \mspace{599mu}} & \; \\{C_{k} = {\frac{1}{2\pi}{\int_{- \pi}^{\pi}{{\exp \left\lbrack {{j \cdot \left( \frac{\omega}{T_{s}} \right)^{2} \cdot \frac{C}{2\pi \; f^{2}} \cdot \frac{D}{2}} + {{j\omega}\; k}} \right\rbrack}\ {\omega}}}}} & (1)\end{matrix}$

FIG. 4B illustrates a block diagram for describing details of the fixeddistortion compensator 81 in a frequency range with use of FFT (FastFourier Transform). As illustrated in FIG. 4B, for example, the FFT typeof the fixed distortion compensator 81 includes a FFT portion 21, arotator multiplication portion 22 and an IFFT portion 23.

A signal input into the fixed distortion compensator 81 is subjected toFast Fourier Transform in the FFT portion 21. The rotator multiplicationportion 22 multiplies the signal subjected to Fast Fourier Transform bya rotator according to transfer function H_(CD) of chromatic dispersionof the frequency range. The transfer function H_(CD) is shown as thefollowing equation (2). The output signal of the rotator multiplicationportion 22 is subjected to a reverse Fourier Transform in the IFFTportion 23. Thus, the fixed distortion compensator 81 compensates forchromatic dispersion with respect to the input signal.

In the equation (2), “f” is a carrier frequency, “C” is a light speed,“D” is a chromatic dispersion compensation amount, “ω” is an angularfrequency, and “j” is an imaginary unit.

$\begin{matrix}{\left\lbrack {{Equation}\mspace{14mu} (2)} \right\rbrack \mspace{599mu}} & \; \\{{H_{CD}(\omega)} = ^{- {j{({\frac{C \times D}{4\pi \; f^{2}}\omega^{2}})}}}} & (2)\end{matrix}$

FIGS. 5A through 5K illustrate an example of a case where the fixeddistortion compensator 81 is a circuit compensating for chromaticdispersion. FIG. 5A illustrates an example of the phase shift detector80 of FIG. 1. FIG. 5B through FIG. 5K illustrate a constellation diagramof a received optical signal and an output of the fixed distortioncompensator in a case where transmission path chromatic dispersion is 0ps/nm and 200 ps/nm, in a case of Quadrature Phase Shift Keying (QPSK).

The phase shift detector 80 of FIG. 5A has four fixed distortioncompensators 81 a through 81 d and four phase shift detectors 82 athrough 82 d. The chromatic dispersion compensation amount of each ofthe fixed distortion compensators 81 through 81 d is 0 ps/nm, 100 ps/nm,200 ps/nm and 300 ps/nm.

FIG. 5B illustrates a waveform of a received optical signal havingchromatic dispersion amount of 0 ps/nm. The chromatic dispersioncompensation amount of the fixed distortion compensator 81 a is 0 ps/nm(=chromatic dispersion amount of the received optical signal).Therefore, the output waveform of the fixed distortion compensator 81 ais the same as FIG. 5B, as illustrated in FIG. 5C. The chromaticdispersion compensation amount of the fixed distortion compensator 81 bis 100 ps/nm (≠ the chromatic dispersion amount of the received opticalsignal). Therefore, the output waveform of the fixed distortioncompensator 81 b is distorted compared to the fixed distortioncompensator 81 a as illustrated in FIG. 5D. As illustrated in FIG. 5Eand FIG. 5F, the output waveform of the fixed distortion compensator isdistorted as a difference between the chromatic dispersion of thereceived optical signal and the chromatic dispersion compensation amountgets larger.

FIG. 5G illustrates a waveform of the received optical signal having thechromatic dispersion of 200 ps/nm. The chromatic dispersion compensationamount of the fixed distortion compensator 81 a is 0 ps/nm (≠ thechromatic dispersion amount of the received optical signal). Therefore,the output waveform of the fixed distortion compensator 81 a isdistorted as illustrated in FIG. 5H. As illustrated in FIGS. 5I and 5K,the distortion of the output waveform of the fixed distortioncompensator is reduced as the difference between the chromaticdispersion compensation amount of the fixed distortion compensator 81 band the fixed distortion compensator 81 d and the chromatic dispersionamount of the received optical signal gets smaller. The chromaticdispersion compensation amount of the fixed distortion compensator 81 cis equal to the wavelength distortion amount of the received opticalsignal. Therefore, the output waveform of the fixed distortioncompensator 81 c is the same as FIG. 5G as illustrated in FIG. 5J.

The chromatic dispersion compensation amount of each fixed distortioncompensator is different from each other. Therefore, the waveformdistortion of the signal output by the fixed distortion compensators 81a through 81 d is different from each other. The type of the fixeddistortion compensators 81 a through 81 d and a step size of thechromatic dispersion compensation amount are determined according to thedispersion tolerance of the phase shift detector circuit 82.

There is a case where the H-polarized wave and the V-polarized wave havea different chromatic dispersion distortion because of a high orderpolarization mode dispersion. In this case, a different chromaticdispersion compensation amount is applied to the H-polarized wave andthe V-polarized wave. For example, a circuit determining dispersioncompensation amount may use only the H-polarized wave. A compensationcircuit of which dispersion compensation amount is 0 ps/nm may beomitted.

There is a case where there is a demand for chromatic dispersioncompensation, polarization mode dispersion (DGD: Differential GroupDelay) compensation and polarized wave division as the waveformdistortion compensation. FIG. 6 illustrates an example of the fixeddistortion compensator 81 in the case. As illustrated in FIG. 6, each ofthe fixed distortion compensators 81 includes four FIR filters 24 athrough 24 d and two addition portions 25 a and 25 b. The FIR filters 24a through 24 d have the same structure as the FIR type fixed distortioncompensator described in FIG. 4A.

The H-I signal and the H-Q signal obtained through the polarized wavedivision at a polarization beam splitter or the like are input into theFIR filter 24 a and the FIR filter 24 c. The V-I signal and the V-Qsignal obtained through the polarized wave division are input into theFIR filter 24 b and the FIR filter 24 d. The FIR filters 24 a through 24d output a result subjected to the distortion compensation. The additionportion 25 a adds an output signal of the FIR filter 24 a to an outputsignal of the FIR filter 24 b, and outputs a signal subjected to theaddition. The addition portion 25 b adds an output signal of the FIRfilter 24 c to an output signal of the FIR filter 24 d, and outputs asignal subjected to the addition.

The dispersion is compensated by setting multiplication coefficients ofmultiplication portions included in the FIR filters 24 a through 24 d tobe different from each other. The DGD compensation and the polarizedwave division are achieved at a desirable angle by optimizing themultiplication coefficients of the multiplication portions included inthe FIR filters 24 a through 24 d.

Next, a description will be given of details of the phase shift detectorcircuit 82. For example, a description will be given of a Gardner typeof phase shift detector circuit disclosed in F. M. Gardner, Trans.Comm., 1986, pp. 423-429. FIG. 7 illustrates a block diagram of thephase shift detector circuit 82. As illustrated in FIG. 7, the phaseshift detector circuit 82 includes a first delay portions 31 a and 31 b,a second delay portions 32 a and 32 b, a subtraction portions 33 a and33 b, a multiplication portions 34 a and 34 b, an addition portion 35, adelay portion 36, a selection portion 37 and a counter 38.

The first delay portions 31 a and 31 b and the delay portion 36 are adelay portion setting a delay amount that is one symbol of an inputsignal. The second delay portions 32 a and 32 b are a delay portionsetting a delay amount that is two symbols of an input signal. Thecounter 38 is a one-bit counter, and generates “0” and “1” in order. Theselection portion 37 selects an output signal according to a signal fromthe counter 38. The phase shift detector circuit 82 is made on anassumption that an input I-phase signal and an input Q-phase signal aresampled twice in one symbol time.

The I-phase signal is input to a minus side of the subtraction portion33 a and is input to the first delay portion 31 a and the second delayportion 32 a. The first delay portion 31 a sets one symbol delay amounton the I-phase signal and inputs the signal into the multiplicationportion 34 a. The second delay portion 32 a sets two symbols delayamount on the I-phase signal and inputs the signal into a plus side ofthe subtraction portion 33 a. The subtraction portion 33 a subtracts theI-phase signal from a signal input from the second delay portion 32 a,and inputs the subtraction result into the multiplication portion 34 a.The multiplication portion 34 a multiplies the signal input from thefirst delay portion 31 a by the signal input from the subtractionportion 33 a, and inputs the multiplication result into the additionportion 35.

The Q-phase signal is input to a minus side of the subtraction portion33 b and is input to the first delay portion 31 b and the second delayportion 32 b. The first delay portion 31 b sets one symbol delay amounton the Q-phase signal and inputs the signal into the multiplicationportion 34 b. The second delay portion 32 b sets two symbols delayamount on the Q-phase signal and inputs the signal into a plus side ofthe subtraction portion 33 b. The subtraction portion 33 b subtracts theQ-phase signal from a signal input from the second delay portion 32 b,and inputs the subtraction result into the multiplication portion 34 b.The multiplication portion 34 b multiplies the signal input from thefirst delay portion 31 b by the signal input from the subtractionportion 33 b, and inputs the multiplication result into the additionportion 35.

The addition portion 35 adds the multiplication result of themultiplication portion 34 a to the multiplication result of themultiplication portion 34 b, and inputs the addition result into thedelay portion 36 and the selection portion 37. The delay portion 36 setsone symbol delay on the signal input from the addition portion 35, andinput the signal into the selection portion 37. The selection portion 37outputs one of the output value of the addition portion 35 and theoutput value of the one symbol delay portion 36, only when a signalinput from the counter 38 is “1”. The output signal of the selectionportion 37 is a value according to a phase shift amount between themodulation frequency of the received optical signal and the samplingclock frequency. The smaller the phase shift amount is, the closer tozero the output value is.

FIG. 8 illustrates a block diagram for describing details of a FIR typeof the phase adjusting circuit 50. As illustrated in FIG. 8, forexample, the phase adjusting circuit 50 includes a first multiplicationportion 51, a second multiplication portion 52, a third multiplicationportion 53, a first delay portion 54, a second delay portion 55, anaddition portion 56, and a coefficient calculation portion 57. The firstmultiplication portion 51, the second multiplication portion 52, and thethird multiplication portion 53 have a multiplication coefficient set bythe coefficient calculation portion 57.

The first delay portion 54 sets a given delay amount on a signal inputto the phase adjusting circuit 50, and outputs the signal. The seconddelay portion 55 sets a given delay amount on a signal output by thefirst delay portion 54, and outputs the signal. The first multiplicationportion 51 multiplies the signal input to the phase adjusting circuit 50by the multiplication coefficient set in the first multiplicationportion 51, and inputs the multiplication result into the additionportion 56. The second multiplication portion 52 multiplies a signaloutput by the first delay portion 54 by the multiplication coefficientset in the second multiplication portion 52, and inputs themultiplication result into the addition portion 56. The thirdmultiplication portion 53 multiplies a signal output by the second delayportion 55 by the multiplication coefficient set in the thirdmultiplication portion 53, and input the multiplication result into theaddition portion 56. The addition portion 56 calculates a total of themultiplication results of the first multiplication portion 51, thesecond multiplication portion 52 and the third multiplication portion53, and outputs the total.

The coefficient calculation portion 57 calculates the multiplicationcoefficients of the first multiplication portion 51, the secondmultiplication portion 52 and the third multiplication portion 53according to the phase adjusting amount of the phase adjusting circuit50. Each of the calculated multiplication coefficients is set in thefirst multiplication portion 51, the second multiplication portion 52and the third multiplication portion 53. Therefore, the phase adjustingcircuit 50 sets the phase adjusting amount on a signal input thereto.The multiplication coefficient is calculated with a linearinterpolation, a quadratic function, or a higher order interpolationequation.

In the embodiment, a plurality of the fixed distortion compensators 81on which a different distortion amount is set are used. This allows asolution of the problem that the phase shift detector circuit has lowtolerance with respect to the waveform distortion. Therefore, a samplingphase shift detecting having high tolerance with respect to the waveformdistortion of the received optical signal is achieved. And, the samplingphase shift is reduced.

The smaller the waveform distortion of a signal input to the phase shiftdetector circuit 82 is, the higher the detection sensitivity of thephase shift detector circuit 82 is. In contrast, the larger the waveformdistortion is, the lower the detection sensitivity of the phase shiftdetector circuit 82 is. Accordingly, the detection sensitivity of thephase shift detector circuit 82 gets lower when the distortion amount ofthe signal input to the fixed distortion compensator 81 is differentfrom the compensation amount of the fixed distortion compensator 81. Andso, a description will be given of a case where a phase shift isdetected based on the detection sensitivity of the phase shift detectorcircuit 82.

FIG. 9A illustrates a block diagram of a sensitivity detector 110detecting sensitivity with use of the phase shift detector circuit 82.As illustrated in FIG. 9A, the sensitivity detector 110 includes a fixedphase adjusting circuit 91, a first phase shift detector circuit 82 e, asecond phase shift detector circuit 82 f, an amplitude monitor 92, and asubtraction portion 93.

The fixed phase adjusting circuit 91 adds a fixed phase amount X to asignal input to the sensitivity detector 110 and outputs the additionresult. The first phase shift detector circuit 82 e and the second phaseshift detector circuit 82 f have the same structure as the phase shiftdetector circuit 82. A signal input to the sensitivity detector 110 isinput to the first phase shift detector circuit 82 e. A signal from thefixed phase adjusting circuit 91 is input to the second phase shiftdetector circuit 82 f. The output signal of the first phase shiftdetector circuit 82 e is input to the amplitude monitor 92 and is inputto a plus side of the subtraction portion 93. The output signal of thesecond phase shift detector circuit 82 f is input to a minus side of thesubtraction portion 93.

The amplitude monitor 92 detects amplitude of a signal output by thefirst phase shift detector circuit 82 e, and outputs the detectedamplitude. The subtraction portion 93 subtracts the output signal of thesecond phase shift detector circuit 82 f from the output signal of thefirst phase shift detector circuit 82 e, and outputs the subtractionresult.

FIG. 9B illustrates an output of the sensitivity detector 110. In FIG.9B, a horizontal axis indicates a phase shift, and a vertical axisindicates an output intensity of the phase shift detector circuit. Theoutput intensity fluctuates according to the phase shift amount. Whenthe phase shift amount is zero, the output intensity is zero.

Here, it is assumed that the phase shift of a signal input to thesensitivity detector 110 is zero. In this case, as illustrated in FIG.9B, the output intensity of the first phase shift detector circuit 82 eis zero, too. The output intensity of the second phase shift detectorcircuit 82 f is a plus value as illustrated in FIG. 9B, because thefixed phase amount X is added in the fixed phase adjusting circuit 91.Thus, output intensity difference or an inclination of the outputintensity is detected as sensitivity.

There is a case where a difference between the output intensity of thefirst phase shift detector circuit 82 e and the output intensity of thesecond phase shift detector circuit 82 f is zero as illustrated in FIG.9B even if the fixed phase amount X is added in the fixed phaseadjusting circuit 91, when the sampling phase is not synchronized withthe modulation frequency of the received optical signal. In this case,the detected sensitivity gets smaller even if a signal input to thesensitivity detector 110 has a phase shift. And so, the detection resultof the amplitude monitor 92 is used in order to detect the sensitivity.

FIG. 9C illustrates a detection result of the amplitude monitor 92. InFIG. 9C, a horizontal axis indicates an elapsed time, and a verticalaxis indicates detection sensitivity of the phase shift detectorcircuit. The detection sensitivity of the sensitivity detector 110 isapproximately constant, when the phase shift between the sampling clockof the sampling clock source 70 and the modulation frequency of thereceived optical signal. On the other hand, the detection sensitivity ofthe sensitivity detector 110 fluctuates periodically, when the samplingclock of the sampling clock source 70 is not synchronized with themodulation frequency of the received optical signal. The amplitudemonitor 92 detects the amplitude value as the detection sensitivity.

For example, the combining circuit 83 of FIG. 3 may average the outputvalues of phase shift detector circuits 82 other than a phase shiftdetector circuit 82 detecting sensitivity that is lower than apredetermined value. In this case, it is possible to avoid an effectsuch as a noise caused by reduction of a phase-shift-detectionsensitivity caused by large waveform distortion. And, the phase shiftdetection accuracy gets higher. Alternatively, thephase-adjusting-amount determiner 90 may detect the sampling phase shiftbased on the output of the phase shift detector circuit 82 detecting themaximum sensitivity.

[b] Second Embodiment

FIG. 10 illustrates a block diagram of a phase shift detector 80 a inaccordance with a second embodiment. As illustrated in FIG. 10, thephase shift detector 80 a has n variable distortion compensators 84instead of the n fixed distortion compensators 81. The phase shiftdetector 80 a has m (m is an integer and is two or more) number of fixeddistortion compensators 86, m number of sensitivity detectors 87 and amaximum sensitivity detector 88. The same components have the samereference numerals in order to avoid a duplicated explanation. In theembodiment, the maximum sensitivity detector 88 acts as a compensationamount detector, and the variable distortion compensator 84 acts as acompensation amount corrector.

Each of the variable distortion compensators 84 receives a H-I signal, aH-Q signal, a V-I signal and a V-Q signal. The signals input to one ofthe variable distortion compensators 84 is input to each of the fixeddistortion compensators 86. The fixed distortion compensator 86 has thesame structure as the fixed distortion compensator 81 of FIG. 3.

Each of the sensitivity detectors 87 detects sensitivity of a signaloutput by the fixed distortion compensator 86. The maximum sensitivitydetector 88 detects a maximum sensitivity of sensitivities detected byeach sensitivity detector 87, and thereby detects a distortioncompensation amount according to the maximum sensitivity. The maximumsensitivity detector 88 inputs the distortion compensation amount intoeach variable distortion compensator 84. Each of the variable distortioncompensators 84 updates the distortion compensation amount into thedistortion compensation amount input from the maximum sensitivitydetector 88. Each of the variable distortion compensator 84 compensatesfor waveform distortion based on the updated distortion compensationamount. Each of the phase shift detector circuit 82 detects a phaseshift of a signal output by each variable distortion compensator 84, andinputs the detected phase shift into the combining circuit 83. Thecombining circuit 83 averages signals input thereto. The combiningcircuit 83 may be a circuit that simply averages the input signals or acircuit that weighted-averages the input signals.

In the embodiment, a compensation amount of the variable distortioncompensator 84 is determined with a feed forward control. Therefore, thelight receiving device 100 speedily conforms the fluctuation of thewaveform distortion of the received optical signal. In the embodiment,the maximum sensitivity detector 88 detects the maximum sensitivity ofthe sensitivities detected by each of the sensitivity detector 87.However, the structure is not limited. For example, any sensitivitylarger than a given value may be detected instead of the maximumsensitivity.

Modified Embodiment

The phase shift detector 80 a may have a parallelizer 85. FIG. 11illustrates an example where the parallelizer 85 is provided. In FIG.11, the parallelizer 85 is provided inside of the phase shift detector80 a. However, the parallelizer 85 may be arranged just behind theanalog/digital converters 40 a through 40 d. In this case, the phaseadjusting circuit 50 and the detector circuit 60 process with aparallelized signal.

The parallelizer 85 parallelizes four signals of the H-I signal, the H-Qsignal, the V-I signal and the V-Q signal with a time division method orthe like. In FIG. 11, the parallelizer 85 parallelizes each of the foursignals into n signals with a time division method, and inputs eachparallelized signal into each variable distortion compensator 84. One ofthe parallelized signals is input to each fixed distortion compensator86. With the modified embodiment, it is possible to reduce a circuitsize of a distortion compensation circuit that is enlarged because ofparallelization of a signal.

[c] Third Embodiment

FIG. 12 illustrates a block diagram of a light receiving device 100 a inaccordance with a third embodiment. As illustrated in FIG. 12, the lightreceiving device 100 a is different from the light receiving device 100of FIG. 1 in a point that the feed back value of thephase-adjusting-amount determiner 90 is input to the sampling clocksource 70. The sampling clock source 70 corrects the sampling clockfrequency according to the feed back value of the phase-adjusting-amountdeterminer 90. Thereby, a phase difference between the sampling clock ofthe analog/digital converter 40 a through 40 d and the modulationfrequency of the received optical signal is reduced. In the embodiment,the phase adjusting circuit 50 compensates for phase fluctuation of themodulation frequency of a high-speed received optical signal that is notsynchronized through the sampling clock frequency control. However, onlythe phase-adjusting-amount determiner 90 may be feed-back controlledwith respect to the sampling clock source 70 without a feed-back controlof the phase-adjusting-amount determiner 90 with respect to the phaseadjusting circuit 50.

[d] Fourth Embodiment

FIG. 13 illustrates a block diagram of a light receiving device 100 b inaccordance with a fourth embodiment. As illustrated in FIG. 13, thelight receiving device 100 b is different from the light receivingdevice 100 of FIG. 1 in a point that a semi-fixed digital filter 120 isprovided between the analog/digital converters 40 a through 40 d and thephase adjusting circuit 50 and in a point that an adaptive equalizationtype digital filter 130 is provided between the phase adjusting circuit50 and the detector circuit 60.

The semi-fixed digital filter 120 compensates for a transmission pathchromatic dispersion that does not fluctuate greatly. It is thereforepossible to receive a distortion caused by large chromatic dispersion.The adaptive equalization type digital filter 130 compensates forresidual chromatic dispersion in the semi-fixed digital filter 120,waveform distortion fluctuating in time (polarization mode dispersion,polarization fluctuation or the like). The chromatic dispersionprocessed in the adaptive equalization type digital filter 130 or thephase shift detector 80 is the residual chromatic dispersion of thesemi-fixed digital filter. Therefore, the circuit size is reduced.

The variable distortion compensator 84 of the phase shift detector 80 ain accordance with the second embodiment may be used in the fourthembodiment if an optimal distortion compensation value of the phaseshift detector 80 is set on the semi-fixed digital filter 120.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various change, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

1. A light receiving device comprising: a converter to digitalize ananalog signal with a given sampling clock frequency, the analog signalbeing obtained through a photoelectric conversion of a received opticalsignal; a plurality of fixed distortion compensators to compensate anoutput signal of the converter for waveform distortion with a fixedcompensation amount that is different from each other; a plurality ofphase shift detector circuits to detect a sampling phase shift from anoutput signal of the plurality of the fixed distortion compensators; aphase-adjusting-amount determiner to determine a sampling phaseadjusting amount with use of an output signal of the plurality of thephase shift detector circuits; and a phase adjusting circuit to reduce aphase difference between the sampling clock frequency and the receivedoptical signal based on a determination result of thephase-adjusting-amount determiner.
 2. A light receiving devicecomprising: a converter to digitalize an analog signal with a givensampling clock frequency, the analog signal being obtained through aphotoelectric conversion of a received optical signal; a plurality offixed distortion compensators to compensate an output signal of theconverter for waveform distortion with a fixed compensation amount thatis different from each other; a plurality of compensation amountdetector to detect a distortion compensation amount based on aphase-shift-detection sensitivity of each output signal of the pluralityof the fixed distortion compensators; a distortion compensator tocompensate for distortion with a distortion compensation amount detectedby the compensation amount detector; a phase-adjusting-amount determinerto determine a sampling phase adjusting amount with use of an outputsignal of the phase shift detector circuit; and a phase adjustingcircuit to reduce a phase difference between the sampling clockfrequency and the received optical signal based on a determinationresult of the phase-adjusting-amount determiner.
 3. The light receivingdevice as claimed in claim 2 further comprising a semi-fixed digitalfilter to compensate an output signal of the converter for waveformdistortion, wherein: compensation amount of the semi-fixed digitalfilter is corrected based on a compensation amount detected by thecompensation amount detector; and the plurality of the fixed distortioncompensators compensate an output signal of the semi-fixed digitalfilter for waveform distortion with a fixed compensation amount that isdifferent from each other.
 4. The light receiving device as claimed inclaim 1, wherein the fixed distortion compensator compensates forchromatic dispersion as the wavelength distortion compensation.
 5. Thelight receiving device as claimed in claim 2, wherein the fixeddistortion compensator compensates for chromatic dispersion as thewaveform distortion compensation.
 6. The light receiving device asclaimed in claim 1, wherein the phase adjusting circuit includes adigital phase adjusting circuit adjusting a phase of an output signal ofthe converter.
 7. The light receiving device as claimed in claim 2,wherein the phase adjusting circuit includes a digital phase adjustingcircuit adjusting a phase of an output signal of the converter.
 8. Thelight receiving device as claimed in claim 1, wherein the phaseadjusting circuit includes a corrector correcting a sampling clockfrequency of the converter.
 9. The light receiving device as claimed inclaim 2, wherein the phase adjusting circuit includes a correctorcorrecting a sampling clock frequency of the converter.
 10. A lightreceiving method comprising: digitalizing an analog signal with a givensampling clock frequency, the analog signal being obtained through aphotoelectric conversion of a received optical signal; compensating anoutput signal obtained in the digitalizing for waveform distortion witha fixed compensation amount that is different from each other; detectinga sampling phase shift from each output signal obtained in thecompensating; determining a sampling phase adjusting amount with use ofan output signal obtained in the detecting; and reducing a phasedifference between the sampling clock frequency and the received opticalsignal based on a determination result of the determining.
 11. A lightreceiving method comprising: digitalizing an analog signal with a givensampling clock frequency, the analog signal being obtained through aphotoelectric conversion of a received optical signal; compensating anoutput signal obtained in the digitalizing for waveform distortion witha fixed compensation amount that is different from each other; detectinga distortion compensation amount based on a phase-shift-detectionsensitivity of each output signal obtained in the compensating for thewaveform; compensating for distortion with a distortion compensationamount detected in the detecting; determining a sampling phase shiftamount with use of an output signal obtained in the compensating for thedistortion; and reducing a phase difference between the sampling clockfrequency and the received optical signal based on a determinationresult of the determining.
 12. The light receiving method as claimed inclaim 11 further comprising correcting compensation amount of asemi-fixed digital filter compensating an output signal obtained in theconverting for waveform distortion with a compensation amount detectedin the detecting, wherein waveform distortion is compensated for withrespect to an output signal of the semi-fixed digital filter with afixed compensation amount that is different from each other in thecompensating for the waveform.
 13. The light receiving method as claimedin claim 11 further comprising adjusting a phase of a signal obtained inthe converting.
 14. The light receiving method as claimed in claim 12further comprising adjusting a phase of a signal obtained in theconverting.
 15. The light receiving method as claimed in claim 11,wherein chromatic dispersion is compensated for as waveform distortioncompensation in the compensating for the waveform.
 16. The lightreceiving method as claimed in claim 12, wherein chromatic dispersion iscompensated for as waveform distortion compensation in the compensatingfor the waveform.
 17. The light receiving method as claimed in claim 11further comprising correcting a sampling clock frequency in theconverting based on a determination result of the determining.
 18. Thelight receiving method as claimed in claim 12 further comprisingcorrecting a sampling clock frequency in the converting based on adetermination result of the determining.